View W25P022AD-6_3243358.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w25p022a 64k 32 burst pipelined high-speed cmos static ram publication release date: september 1996 - 1 - revision a1 general description the w25p022a is a high-speed, low-power, synchronous-burst pipelined cmos static ram organized as 65,536 32 bits that operates on a single 3.3-volt power supply. a built-in two-bit burst address counter supports both pentium ? burst mode and linear burst mode. the mode to be executed is controlled by the lbo pin. pipelining or non-pipelining of the data outputs is controlled by the ft pin. a snooze mode reduces power dissipation. the w25p022a supports both 2t/2t mode and 2t/1t mode, which can be selected by pin 42. the default mode is 2t/1t, with pin 42 low. to switch to 2t/2t mode, bias pin 42 to v ddq . the state of pin 42 should not be changed after power up. the 2t/2t mode will sustain one cycle of valid data output in a burst read cycle when the device is deselected by ce2/ ce3 . this mode supports 3-1-1-1- 1-1-1-1 in a two-bank, back-to-back burst read cycle. on the other hand, the 2t/1t mode disables data output within one cycle in a burst read cycle when the device is deselected by ce2/ ce3 . in this mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle. features synchronous operation high-speed access time: 6/7 ns (max.) single +3.3v power supply individual byte write capability 3.3v lvttl compatible i/o clock-controlled and registered input asynchronous output enable pipelined/non-pipelined data output capability supports snooze mode (low-po wer state) internal burst counter supports intel burst mode & linear burst mode supports both 2t/2t & 2t/1t mode packaged in 100-pin qfp or tqfp block diagram a(15:0) data i/o register input register control logic registe r 64k x 32 core array ce(3:1) bwe clk oe gw adsc adsp adv lbo bw(4:1) i/o(32:1) ft zz ms
w25p022a - 2 - pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 80 79 78 77 76 75 74 73 72 71 70 69 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 0 0 a 6 a 7 / c e 1 c e 2 / b w 4 / b w 3 / b w 2 / b w 1 / c e 3 v d d v s s c l k / g w / b w e / o e / a d s c / a d s p / a d v a 8 a 9 nc i/o 16 i/o 15 vddq vssq i/o 14 i/o 13 i/o 12 i/o 11 vssq vddq i/o 10 i/o 9 vss nc vdd zz i/o 8 i/o 7 vddq vssq i/o 6 i/o 5 i/o 4 i/o 3 vssq vddq i/o 2 i/o 1 nc nc i/o 17 i/o 18 vddq vssq i/o 19 i/o 20 i/o 21 i/o 22 vssq vddq i/o 23 i/o 24 /ft vdd nc vss i/o 25 i/o 26 vddq vssq i/o 27 i/o 28 i/o 29 i/o 30 vssq vddq i/o 31 i/o 32 nc / l b o a 5 a 4 a 3 a 2 a 1 a 0 n c n c v s s v d d n c m s a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 n c 100-pin tqfp mo-136 qfp mo-108 a 1 5
w25p022a publication release date: september 1996 - 3 - revision a1 pin description symbol type description a0 - a15 input, synchronous host address i/o1 - i/o32 i/o, synchronous data inputs/outputs clk input, clock processor host bus clock ce1 , ce2, ce3 input, synchronous chip enables gw input, synchronous global write bwe input, synchronous byte write enable from cache controller bw1 - bw4 input, synchronous host bus byte enables used with bwe oe input, asynchronous output enable input adv input, synchronous internal burst address counter advance adsc input, synchronous address status from chip set adsp input, synchronous address status from cpu zz input, asynchronous snooze pin for low-power state, internally pulled low ft input, static connected to v ssq : device operates in flow-through (non-pipelined) mode. connected to v ddq or unconnected: device operates in piplined mode. lbo input, static lower address burst order connected to v ssq : device operates in linear mode. connected to v ddq or unconnected: device is in non- linear mode. ms input, static mode select for 2t/2t or 2t/1t when unconnected or pulled low, device is in 2t/1t mode; if pulled high (v ddq ), device enters 2t/2t mode. v ddq i/o power supply v ssq i/o ground v dd power supply v ss ground nc no connection
w25p022a - 4 - truth table cycle address used ce1 ce2 ce3 adsp adsc adv oe data write* unselected no 1 x x x 0 x x hi-z x unselected no 0 x 1 0 x x x hi-z x unselected no 0 0 x 0 x x x hi-z x unselected no 0 x 1 1 0 x x hi-z x unselected no 0 0 x 1 0 x x hi-z x begin read external 0 1 0 0 x x x hi-z x begin read external 0 1 0 1 0 x x hi-z read continue read next x x x 1 1 0 1 hi-z read continue read next x x x 1 1 0 0 d-out read continue read next 1 x x x 1 0 1 hi-z read continue read next 1 x x x 1 0 0 d-out read suspend read current x x x 1 1 1 1 hi-z read suspend read current x x x 1 1 1 0 d-out read suspend read current 1 x x x 1 1 1 hi-z read suspend read current 1 x x x 1 1 0 d-out read begin write current x x x 1 1 1 x hi-z write begin write current 1 x x x 1 1 x hi-z write begin write external 0 1 0 1 0 x x hi-z write continue write next x x x 1 1 0 x hi-z write continue write next 1 x x x 1 0 x hi-z write suspend write current x x x 1 1 1 x hi-z write suspend write current 1 x x x 1 1 x hi-z write notes: 1. for a detailed definition of read/write, see the write table below. 2. an "x" means don't care, "1" means logic high, and "0" means logic low. 3. the oe pin enables the data output but is not synchronous with the clock. all signals of the sram are sampled synchronous to the bus clock except for the oe pin. 4. on a write cycle that follows a read cycle, oe must be inactive prior to the start of the write cycle to allow write data to set up the sram. oe must also disable the output buffer prior to the end of a write cycle to ensure the sram data hold timings are m et.
w25p022a publication release date: september 1996 - 5 - revision a1 functional description the w25p022a is a synchronous-burst pipelined sram designed for use in high-end personal computers. it supports two burst address sequences for intel ? systems and linear mode, which can be controlled by the lbo pin. the burst cycles are initiated by adsp or adsc and the burst counter is incremented whenever adv is sampled low. the device can also be switched to non- pipelined mode if necessary. burst address sequence intel system ( lbo = v ddq ) linear mode ( lbo = v ssq ) a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] a[1:0] external start address 00 01 10 11 00 01 10 11 second address 01 00 11 10 01 10 11 00 third address 10 11 00 01 10 11 00 01 fourth address 11 10 01 00 11 00 01 10 the device supports several types of write mode operations. bwe and bw [4:1] support individual byte writes. the be [7:0] signals can be directly connected to the sram bw [4:1]. the gw signal is used to override the byte enable signals and allows the cache controller to write all bytes to the sram, no matter what the byte write enable signals are. the various write modes are indicated in the write table below. note that in pipelined mode, the byte write enable signals are not latched by the sram with addresses but with data. in pipelined mode, the cache controller must ensure the sram latches both data and valid byte enable signals from the processor. write table read/write function gw bwe bw4 bw3 bw2 bw1 read 1 1 x x x x read 1 0 1 1 1 1 write byte 1 i/o1 - i/o8 1 0 1 1 1 0 write byte 2 i/o9 - i/o16 1 0 1 1 0 1 write byte 2, byte 1 1 0 1 1 0 0 write byte 3 i/o17 - i/o24 1 0 1 0 1 1 write byte 3, byte 1 1 0 1 0 1 0 write byte 3, byte 2 1 0 1 0 0 1 write byte 3, byte 2, byte 1 1 0 1 0 0 0 write byte 4 i/o25 - i/o32 1 0 0 1 1 1 write byte 4, byte 1 1 0 0 1 1 0
w25p022a - 6 - write table, continued read/write function gw bwe bw4 bw3 bw2 bw1 write byte 4, byte 2 1 0 0 1 0 1 write byte 4, byte 2, byte 1 1 0 0 1 0 0 write byte 4, byte 3 1 0 0 0 1 1 write byte 4, byte 3, byte 1 1 0 0 0 1 0 write byte 4, byte 3, byte 2 1 0 0 0 0 1 write all bytes i/o1 - i/o32 1 0 0 0 0 0 write all bytes i/o1 - i/o32 0 x x x x x the zz state is a low-power state in which the device consumes less power than in the unselected mode. enabling the zz pin for a fixed period of time will force the sram into the zz state. pulling the zz pin low for a set period of time will wake up the sram again. while the sram is in zz mode, data retention is guaranteed, but the chip will not monitor any input signal except for the zz pin. in the unselected mode, on the other hand, all the input signals are monitored. absolute maximum ratings parameter rating unit core supply voltage to vss -0.5 to 4.6 v i/o supply voltage to vss -0.5 to 4.6 v input/output to v ssq potential v ssq -0.5 to v ddq +0.5 v allowable power dissipation 1.0 w storage temperaure -65 to 150 c operating temperature 0 to +70 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device.
w25p022a publication release date: september 1996 - 7 - revision a1 operating characteristics (v dd /v ddq = 3.15v to 3.6v, v ss / v ssq = 0v, t a = 0 to 70 c) parameter sym. test conditions min. typ . max. unit input low voltage v il - -0.5 - +0.8 v input high voltage v ih - +2.0 - v dd +0.3 v input leakage current i li v in = v ssq to v ddq -10 - +10 m a output leakage current i lo v i/o = v ssq to v ddq, and data i/o pins in high-z state defined in truth table -10 - + 10 m a output low voltage v ol i ol = +8.0 ma - - 0.4 v output high voltage v oh i oh = -4.0 ma 2.4 - - v operating current i dd t cyc 3 min., i/o = 0 ma - - 250 ma standby current i sb unselected mode defined in truth table, v in , v io = v ih (min.) /v il (max.) t cyc 3 min. - - 80 ma zz mode current i zz zz mode, t cyc 3 min. - - 5 ma note: typical characteristics are measured at v dd = 3.3v, t a = 25 c. capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter sym. conditions max. unit input capacitance c in v in = 0v 6 pf input/output capacitance c i/o v out = 0v 8 pf note: these parameters are sampled but not 100% tested. ac test conditions parameter conditions input pulse levels 0v to 3v input rise and fall times 2 ns input and output timing reference level 1.5v output load c l = 30 pf, i oh /i ol = -4 ma/8 ma
w25p022a - 8 - ac test loads and waveform 90% 90% 2 ns 10% 2 ns 10% rl = 50 ohm vl = 1.5v output 5 pf r2 350 ohm r1 320 ohm 3.3v output 30 pf including jig and scope 3.0v 0v including jig and scope zo = 50 ohm (for t khz, t klz, t ohz, t olz, measurement) ac timing characteristics (v dd /v ddq = 3.15v to 3.6v, v ss /v ssq = 0v, t a = 0 to 70 c, all timings measured in pipelined mode) parameter sym. w25p022a-6 w25p022a-7 unit notes min. max. min. max. add. setup time t as 2.5 - 2.5 - ns add. hold time t ah 0.5 - 0.5 - ns write data setup time t ds 2.5 - 2.5 - ns write data hold time t dh 0.5 - 0.5 - ns adv setup time t advs 2.5 - 2.5 - ns adv hold time t advh 0.5 - 0.5 - ns adsp setup time t adss 2.5 - 2.5 - ns adsp hold time t adsh 0.5 - 0.5 - ns adsc setup time t adcs 2.5 - 2.5 - ns adsc hold time t adch 0.5 - 0.5 - ns ce1 , ce2, ce3 setup time t ces 2.5 - 2.5 - ns ce1 , ce2, ce3 hold time t ceh 0.5 - 0.5 - ns gw , bwe x setup time t ws 2.5 - 2.5 - ns gw , bwe x hold time t wh 0.5 - 0.5 - ns
w25p022a publication release date: september 1996 - 9 - revision a1 ac timing characteristics, continued parameter sym. w25p022a-6 w25p022a-7 unit notes min. max. min. max. clock cycle time t cyc 13.3 - 15 - ns clock high pulsh width t kh 5 - 6 - ns clock low pulse width t kl 5 - 6 - ns clock to output valid t kq - 6 - 7 ns clock to output high-z t khz 2 13.3 2 15 ns 1 clock to output low-z t klz 0 - 0 - ns 1 clock to output invalid t kx 2 - 2 - ns 1 output enable to output valid t oe - 6 - 7 ns output enable to output high-z t ohz - 6 - 7 ns 1 output enable to output low-z t olz 0 - 0 - ns 1 output enable to output invalid t ox 0 - 0 - ns zz standby time t zzs - 100 - 100 ns 2 zz recover time t zzr 100 - 100 - ns 3 notes: 1. these parameters are sampled but not 100% tested 2. in the zz mode, the sram will enter a low-power state. in this mode, data retention is guaranteed and the clock is active. 3. adsc and adsp should not be accessed for at least 100 ns after chip leaves zz mode. 4. configuration signals lbo and ft are static and should not be changed during operation.
w25p022a - 10 - timing waveforms read cycle timing 3a 2d 2c 2b 2a 1a single read burst read unselected t cyc clk t adss t adsh t kh t kl adsp is blocked by ce1 inactive t adcs t adch adsc initiated read t advs t advh t as t ah rd1 rd2 rd3 t ws t wh t ws t wh t ces t ceh ce1 masks adsp t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc unselected with ce2 t oe t ohz t olz t ox t kx t khz t kx high-z high-z adsp adsc adv a[15:0] gw bwe bw[4:1] ce1 ce2 ce3 oe data-out data-in t klz t kq pipelined read suspend burst don't care undefined
w25p022a publication release date: september 1996 - 11 - revision a1 timing waveforms, continued write cycle timing 1a single write burst write unselected t cyc clk t adss t adsh t kh t kl adsp is blocked by ce1 inactive t adcs t adch adsc initiated write t advs t advh t as t ah wr1 wr2 wr3 t ws t wh t ws t wh t ces t ceh ce1 masks adsp t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc unselected with ce2 high-z high-z adsp adsc adv a[15:0] gw bwe bw[4:1] ce1 ce2 ce3 oe data-out data-in 2a 2b 2c 2d 3a write gwe allows processor address (and be=bw) to be pipelined during a writeback t ws t wh wr1 wr2 wr3 t ds t dh bw[4:1] are applied only to first cycle of wr2 adv must be inactive for adsp write don't care undefined
w25p022a - 12 - timing waveforms, continued read/write cycle timing 2d 2c 2a 1a single read burst read unselected t cyc clk t adss t adsh t kh t kl adsp is blocked by ce1 inactive t adcs t adch adsc initiated read t advs t advh suspend burst t as t ah rd1 wr1 rd2 t ws t wh t ws t wh t ces t ceh ce1 masks adsp t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc t oe t ohz t olz t oh t khz t kx high-z high-z adsp adsc adv a[15:0] gw bwe bw[4:1] ce1 ce2 ce3 oe data-out data-in t klz t kq single write wr1 t ws t wh unselected with ce3 2b 1a t khz t ds t dh don't care undefined
w25p022a publication release date: september 1996 - 13 - revision a1 timing waveforms, continued zz and rd timing 1a single read snooze -with data retention read t cyc clk t adss t adsh t kh t kl t advs t advh t as t ah rd1 t ws t wh t ws t wh t ces t ceh t ces t ceh t ces t ceh t oe t ohz t olz t oh high-z high-z adsp adsc adv a[15:0] gw bwe bw[4:1] ce1 ce2 ce3 oe data-out data-in t klz t kq rd2 t khz t ws t wh rd rd t kx rd t zzs t zzr zz don't care undefined
w25p022a - 14 - timing waveforms, continued dual-bank burst read cycle clk adsp adsc adv gw bwe bw[4:1] ce1 oe d[63:0] bank 0 don't care undefined select bank 0 select bank 1 1d 1c 1a 1b d[63:0] bank 1 2d 2c 2a 2b ce[3:2] bank 0 ce[3:2] bank 1 a[31:3] read 1 read 2 active non- active active non- active
w25p022a publication release date: september 1996 - 15 - revision a1 ordering information part no. access time ( n s) operating current max. ( m a) standby current max. ( m a) package w25p022af-6 6 250 80 100-pin qfp w25p022af-7 7 250 80 100-pin qfp W25P022AD-6 6 250 80 100-pin tqfp w25p022ad-7 7 250 80 100-pin tqfp notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w25p022a - 16 - package dimensions 100-pin qfp e h e y a a seating plane l l 1 see detail f 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. 0.08 0 7 0 0.003 1.60 0.95 17.40 0.80 17.20 0.65 17.00 0.063 0.037 0.921 0.685 0.031 0.913 0.677 0.025 0.905 0.669 0.65 20.10 14.10 0.20 0.40 2.87 20.00 14.00 2.72 19.90 13.90 0.10 0.20 2.57 0.791 0.555 0.008 0.016 0.113 0.787 0.551 0.107 0.026 0.783 0.547 0.004 0.008 0.101 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.012 0.006 0.15 0.30 23.00 23.20 23.40 7 0.020 0.032 0.498 0.802 0.35 0.25 0.01 0.014 0.018 0.45 q h d d b e 2 1 c 100-pin tqfp e h e y a a seating plane l l 1 see detail f 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. 0.08 0 7 0 0.003 1.00 0.75 16.10 0.60 16.00 0.45 15.90 0.039 0.030 0.870 0.634 0.024 0.866 0.630 0.018 0.862 0.626 0.65 20.10 14.10 0.20 0.38 1.45 20.00 14.00 1.40 19.90 13.90 0.10 0.22 1035 0.791 0.555 0.008 0.015 0.057 0.787 0.551 0.055 0.026 0.783 0.547 0.004 0.009 0.053 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y q a a l 1 1 2 e 0.013 0.006 0.15 0.32 21.90 22.00 22.10 7 0.020 0.032 0.498 0.802 0.10 0.05 0.002 0.004 0.006 0.15 h d d 2 1 b e c
w25p022a publication release date: september 1996 - 17 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792647 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

▲Up To Search▲

Price & Availability of W25P022AD-6

	To Download W25P022AD-6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .